3D DRAM and PCMs in Processor Memory Hierarchy

  • Posted on: 1 March 2015
  • By: awh0047
K. Kavi, S. Pianelli, G. Pisano, G. Regina and M. Ignatowski
Memory hierarchy, 3D DRAMs, PCM, set-associate addressing, energy modeling, memory latency modeling.

In this paper we describe and evaluate two possible architectures using 3D DRAMs and PCMs in the processor memory hierarchy. We explore using (a) 3D DRAM as main memory with PCM as backing store and (b) 3D DRAM as the Last Level Cache and PCM as the main memory. In each of these configurations, since the proposed main memories are significantly faster than today’s off-chip 2D DRAMs for main memory and either flash memory based SSDs or magnetic hard drives for secondary storage, we will introduce hardware assistance for virtual to physical address translation and to speed up page-fault handling. We use Simics, a full system simulator and benchmarks from both SPEC 2006 and OLTP suites to evaluate our designs. Our experiments measure energy consumed and execution performance; we use CACTI for obtaining energy and latency values for our memory configurations.

Publish Date: 
Saturday, February 1, 2014
International Conference on Architecture of Computer Systems (ARCS 2014), pp 183-195
Paper URL: