The emergence of 3D-DRAM has rekindled interest in near-data processing research. This article introduces and describes a method for near-data processing using dataflow
techniques implemented with coarse grain reconfigurable logic. We provide an initial evaluation of the concept to justify further development. The melding of these technologies produces
increased throughput while dramatically reducing energy needs for suitable classes of algorithms. The benchmarks analyzed in this paper show performance speedups of 1.1 to 13.2 with energy reductions of 88% to 99%.